Semiconductors and PCBs Lead U.S. Manufacturing Output at +22% – and the Constraint Has Moved Under the Chip

Two announcements in the same week, aimed at the same layer of the electronics stack, tell you where domestic manufacturing capability actually stands. On October 10, the White House Council of Economic Advisers published The State of American Manufacturing, re-released by the White House on October 22. Buried in its Federal Reserve industrial production section is the number that matters to process and packaging engineers: Semiconductors/Printed Circuit Boards manufacturing output is up 22 percent year over year, an acceleration from the 12 percent rate of the prior year – the fastest-growing category the report charts, ahead of computer and electronic products, machinery, and defense and space equipment.

The surrounding data is consistent: manufacturing employment is up 72,000 in 2026, with durable goods manufacturing up 101,000; the S&P Global U.S. Manufacturing PMI hit 55.9 in September, a fourteenth straight month of expansion; nominal manufacturing wages are up 7.9 percent since January 2025, and 9.2 percent excluding managers. These are Federal Reserve, BLS and S&P data points, and they describe volume. They do not, by themselves, describe capability.

The same week, the money moved under the chip

On October 21 at GTC Berlin, NVIDIA published capacity agreements with six manufacturing partners – Amkor Technology, IBIDEN, King Yuan Electronics (KYEC), Samsung Electro-Mechanics, Siliconware Precision Industries (SPIL) and Unimicron – spanning exactly the layers that sit beneath the die:

  • Substrates: agreements with IBIDEN, Samsung Electro-Mechanics and Unimicron will drive a 2.5x increase in substrate capacity over three years. IBIDEN’s Ono plant targets 3x current capacity, supported by a multibillion-dollar capacity reservation advance, with new capacity ramping from Q1 2028. Unimicron’s Taiwan expansion begins adding capacity in Q2 2027.
  • Advanced packaging: Amkor plans a greater than 300 percent increase in interposer wafer capacity by the end of 2028 – in South Korea.
  • Testing: NVIDIA expects total semiconductor test capacity to double from calendar 2026 to 2027, including a $1.1 billion capacity reservation advance to KYEC for new U.S. testing facilities, with high-volume production targeted for April 2027.
  • Optical engines: SPIL targets a 15x increase in co-packaged optics capacity by mid-2027.

Jensen Huang’s framing was blunt: “Demand is extraordinary. Capacity is the constraint.” Market accounts on X and X carried the same numbers within hours, and supply-chain analysis on X confirmed the prepayment structure behind IBIDEN’s Ono expansion. On October 25, the SemiAnalysis view circulated on X put substrates and advanced PCB materials ahead of memory and optics as the binding constraint on AI infrastructure through 2027 and 2028.

Read the geography carefully. Almost all of that substrate, interposer and optical capacity lands in Japan, South Korea and Taiwan. The one unambiguously domestic line item in the entire announcement is test – KYEC’s April 2027 U.S. high-volume production date. The board-and-package layer is where the demand is hardest, and it is still overwhelmingly offshore.

Why +22 percent is a starting point, not a milestone

The Printed Circuit Board Association of America states the base case plainly: 96 percent of the world’s printed circuit boards are manufactured outside the United States. Growing 22 percent year off a roughly 4 percent global share is real growth compounding from very little – it does not close the capability gap in high-layer-count, high-speed, low-loss board construction, which industry analysis on X noted in early October cannot be relocated overnight.

The procurement clock is running on the same layer. 10 U.S.C. section 4873 – enacted through sections 841 and 851 of the FY2021 and FY2022 National Defense Authorization Acts – prohibits the Department of Defense from acquiring covered printed circuit boards from covered nations beginning January 1, 2027. The Department of War’s July 2, 2026 advance notice of proposed rulemaking sketches a waiver framework grounded in ISO/IEC 20243, IPC-1782 traceability and IPC-1791 Trusted Assembler verification, with mandatory flow-down to every tier of the supply chain; the certification-based framework it describes is a manufacturing and quality undertaking, not a paperwork exercise. The industry association’s September statement opposed delay and broad exemptions. We covered the certification lead-time problem and what it demands of process capability in September; the production data released this month does not change that analysis – it sharpens it. A defense supply-chain assessment published on X in July made the same structural point about missile production: propellants, batteries, PCBs, semiconductors, industrial gases and radome materials, each on its own qualification clock.

What +22 percent actually demands on the process side

If domestic output of boards, substrates and packages is really going to grow at these rates, the constraint moves from capital to process discipline. That shows up concretely on the floor:

  • New capacity is new lines, new laminates and new entrants – and first-article qualification is where domestic sourcing is actually decided. Newly qualified boards and components arrive with oxide, mold release, handling residues and ionic contamination. On high-layer-count, high-impedance and higher-voltage assemblies, electrochemical migration and conductive anodic filament growth are field failures, not yield noise. Cleanliness has to be measured – ion chromatography or ROSE testing against the applicable IPC acceptance criteria – not assumed, and a “no-clean” process has to be verified against the actual flux, board finish and assembly atmosphere rather than inherited from a datasheet.
  • Assembly-side contamination control decides first-pass yield. Stencil and misprint cleaning, controlled solder paste handling, vapor degreasing or aqueous cleaning for post-assembly residue removal, controlled rinse and dry, conformal coating adhesion that depends on a clean and dry surface, underfill fillet quality driven by surface condition – these are the steps that separate a domestically built assembly from a domestically qualified one.
  • Interconnect integrity is a process window, not a machine setting. Die attach and wire bonding on RF/microwave hybrids, power modules and mixed-technology boards need characterized bond windows, pull and shear data, void control, and documented thermal and vacuum profiles for attach, cure and reflow – particularly where void-free bond lines are a reliability requirement.
  • Obsolescence keeps legacy parts in the build for decades. Defense and aerospace platforms run 15-30 year lifecycles; design and material obsolescence means re-sourcing laminates, packages and components, which brings solderability verification, controlled re-tinning, lead forming and cutting, and reconditioning of parts that have sat in storage or moved through alternate channels. A new domestic source has to pass first article like any other.
  • Traceability is a deliverable. The rulemaking framework’s expectation of machine-level IPC-1782 traceability extends beyond the bare board to the processes around it: cleaning records, bath chemistry logs, thermal profiles and rework history are what turn a domestically sourced assembly into a domestically auditable one.
  • Workforce is part of the ramp risk. With manufacturing employment up 72,000 this year and factory construction employment up more than 111,000 since January 2025, new lines are being staffed by new teams. Process discipline is the thing that does not scale automatically with headcount, and its failures surface as field returns two years later.

What to watch next

Four markers separate the growth number from the capability claim: whether Federal Reserve industrial production keeps semiconductors/PCBs at these rates over the next two releases; whether new domestic board capacity – including the ultra-HDI facility opened in Michigan this fall – converts into qualified, audited output rather than installed capacity; what the Department of War’s final rule says after the ANPR comment period closed at the end of August; and whether KYEC’s April 2027 U.S. test facility and IBIDEN’s Q1 2028 Ono ramp arrive on schedule. We tracked the first U.S.-sourced silicon interposers for advanced packaging earlier this month – the same logic applies here: the milestone is real, and the process chain behind it is the hard part.

Akrivis supports U.S. and North American electronics manufacturers building that domestic capability – cleaning and contamination control, PCB/SMT and microassembly cleaning, vapor degreasing, component lead forming and cutting, legacy component reconditioning and tinning, solderability, wire bonding, and thermal and vacuum process equipment, backed by North American application support. Our application engineers work with semiconductor packaging teams, EMS providers, RF/microwave and hybrid microelectronics groups, and aerospace and defense electronics suppliers on the process questions that decide whether a newly domestic board, component or assembly becomes a qualified, field-reliable product.

Request an application review to talk through your cleaning, solderability, bonding, reconditioning or thermal process challenges with an Akrivis application engineer. Visit /contact/ to start.

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