On September 29, 2026, SemiVision on X reported, citing sources in the semiconductor equipment industry, that TSMC is evaluating a major expansion of its U.S. “Made in America” manufacturing footprint. Following its massive Arizona investment, TSMC is said to be planning a second U.S. manufacturing campus — potentially six additional advanced wafer fabs — with Dallas, Texas having emerged as a leading candidate. The reported investment could exceed the US$265 billion committed to Arizona, potentially creating a new “Southern U.S. Semiconductor Dual-Hub Corridor” that connects TSMC’s Arizona advanced wafer base with Texas’s rapidly expanding semiconductor ecosystem — Texas Instruments, Coherent, Samsung, and a North Texas cluster boosters call the Silicon Prairie.
Days later the story gathered corroboration and nuance. East Asia Brief (September 29, 2026) reported, citing the Economic Daily News and supply-chain participants in Taipei, that TSMC has initiated preliminary planning and is prioritizing the Dallas area, with a potential campus of up to six advanced fabs and investment that could match or exceed the $265 billion Phoenix commitment. The report stressed that the plan “has not been finalized”: TSMC has not issued an official statement, no board decision has been announced, no filing has been made with the Taiwan Stock Exchange or the U.S. SEC, and equipment suppliers have not received binding purchase specifications.
Analysts at Herald Business Korea (October 2026) laid out the strategic framing: a “Southern Semiconductor Dual-Hub Corridor” linking Arizona’s advanced wafer manufacturing with Dallas’s established “Silicon Prairie” — TI, Coherent, Samsung, Tesla — offers water, stable electricity, and lower tax burdens, offsetting the challenges (water, power, labor) reported at the Arizona site. As Manufacturing Dive reported in the same mid-October window, the accompanying fab and packaging news — GlobalFoundries selected to operate two new Malta fabs under a U.S.-Japan initiative, plus the first U.S.-based silicon interposer capacity for TSMC’s CoWoS advanced-packaging ecosystem — underlines that the real bottleneck in the domestic supply chain is advanced packaging and downstream process capability, not wafer count.
Six more fabs don’t close the loop — packaging does
It is tempting to read these headlines as a binary: “TSMC is adding another U.S. campus, therefore Made in America is accelerating.” But for the engineers who actually build the electronics, the metric that matters is not the number of fabs tipping over their first wafers — it is whether the process chain downstream of the fab can convert those wafers into qualified, field-reliable packaged components and assemblies onshore.
The semiconductor industry knows this tension better than almost anyone. The most advanced logic die on a U.S. wafer still does not become a finished product until it has been packaged. TSMC’s own Arizona plan pairs wafer fabs with advanced packaging and an R&D center, a recognition that advanced packaging is where the modern bottleneck actually sits. This week’s GlobalFoundries–Commerce CHIPS amendment — reallocating up to $955 million to silicon photonics, silicon-germanium, and advanced packaging, with GF establishing the first U.S.-based silicon interposer source for TSMC’s CoWoS ecosystem — is the same story told from the packaging side:
- Silicon interposers and 2.5D/3D integration. CoWoS-class packages depend on silicon interposers with through-silicon vias, deep-trench capacitors, and controlled bow. Interposer fabrication is a process-capability question — wafer thinning, TSV etch/fill, cleaning, photolithography, and metrology — all steps that must be qualified domestically.
- Cleaning and contamination control. Flux residue, ionic contamination, and particulates from die-attach, reflow, and underfill become latent reliability failures in aerospace, defense, and medical electronics. Vapor degreasing and controlled aqueous/semi-aqueous cleaning with documented process windows are the difference between a package that qualifies and one that fails first article.
- Microassembly and wire bonding. Die placement, wire bond loop control, and bond-pad cleanliness determine yield and long-term reliability. Surface condition after cleaning, tool selection, and qualified process windows are the real variables.
- Component tinning, lead forming, and solderability. Domestic sourcing of alternates and re-sourced legacy parts makes lead finishing and solderability verification (J-STD-002 / J-STD-003) a gating step — especially for defense, aerospace, and long-lifecycle medical programs where component availability is a constraint.
- Thermal and vacuum process control. Cure profiles for adhesives and underfills, vacuum-assisted void control, controlled reflow, and thermal qualification determine whether a domestic package survives thermal cycling in the field.
- Traceability and qualification. “Made in America” today means an enforced, evidence-based claim. Domestic process lines must produce the documentation — process logs, cleaning-bath chemistry and dwell records, bond and thermal profiles, serialized traceability — that lets an integrator actually demonstrate domestic capability to a customer or program.
What a Texas campus would mean for North American electronics manufacturing
A TSMC Dallas campus would be a genuine and welcome expansion of U.S. advanced logic capacity, with a practical next question for every supplier in the corridor: what is the process capability between the wafer and the qualified assembly?
For EMS providers, semiconductor packaging teams, RF/microwave and hybrid microelectronics builders, aerospace/defense electronics suppliers, and medical device manufacturers, the opportunity is to be the step that makes the domestic chip actually usable. That means proving out, onshore, the process disciplines that were historically offshored with the packaging chain:
- Advanced packaging cleaning — flux removal after die-attach and reflow, underfill residue control, and ionic cleanliness verification.
- Vapor degreasing — solvent-based cleaning for components and assemblies where water-based processing risks entrapment or material incompatibility.
- PCB/SMT and microassembly cleaning — post-reflow flux removal with contamination-control characterization.
- Lead forming, cutting, and reconditioning — through-hole and gull-wing lead prep, legacy component reconditioning, and solderability restoration for alternate-sourced parts.
- Wire bonding and interconnects — qualified wire bond process capability with documented bond-shear and pull data.
- Component tinning and solderability — controlled re-tinning and solderability verification for components entering domestic assembly lines.
- Thermal and vacuum process equipment — cure, bake, vacuum and controlled thermal processing for adhesives, encapsulants, and thin-film substrates.
The honest caveat
None of this is a done deal. TSMC has not confirmed the Dallas plan, its board has not approved it, no equipment supplier has received a binding purchase order, and no capital commitment has been filed. The reported project also depends on an extension of the CHIPS Act 35% advanced-manufacturing tax credit that expires at the end of 2026. The credible reading is that TSMC is seriously evaluating a second U.S. campus in the Dallas area — and the fact that a second campus is even being evaluated is itself a signal of how far the U.S. reshoring push has moved in two years.
The reminder it carries for every engineering team, though, is the same one the week’s other announcements carry: domestic wafer capacity is not yet domestic electronics capability. The packaging, assembly, cleaning, and process-qualification step remains the strategic gap — and it is exactly where process-capability partners like Akrivis operate.
Akrivis supports the domestic process chain
Akrivis is a North American supplier of specialized electronics manufacturing process equipment. We support U.S. and North American manufacturers building domestic electronics capability — precision cleaning and contamination control, PCB/SMT and microassembly cleaning, vapor degreasing, component tinning and solderability restoration, lead forming and cutting, legacy component reconditioning, wire bonding, thermal and vacuum process equipment, and North American application support.
Akrivis does not claim its equipment is Made in USA, Buy American compliant, or federally compliant unless independently verified for a specific program; those determinations are procurement-specific. What we can do is help your team build the documented process capability that a credible domestic supply chain actually requires.
Request an Application Review — If your team is qualifying domestic packaging, advanced assembly, cleaning, or process capability for defense, aerospace, medical, or high-reliability programs, our application engineers can walk through your contamination-control, soldering, thermal, and vacuum process needs. Contact Akrivis →
Sources
- SemiVision on X (September 29, 2026) — sources in the semiconductor equipment industry report TSMC evaluating a second U.S. campus, up to six fabs, Dallas a leading candidate, potential “Southern U.S. Semiconductor Dual-Hub Corridor.”
- East Asia Brief (September 29, 2026) — TSMC weighs second US chip hub in Texas; preliminary planning underway, Dallas-area site, not finalized, no board decision or SEC/TWSE filing.
- Herald Business Korea (October 2026) — “Southern Semiconductor Dual-Hub Corridor” strategic framing; Texas Silicon Prairie cluster (TI, Coherent, Samsung, Tesla).
- Manufacturing Dive (October 14, 2026) — GlobalFoundries selected to operate two new $21B Malta fabs under U.S.-Japan initiative; advanced packaging and interposer context.