Last week, Bosch announced it has begun sample production of silicon carbide (SiC) chips at its Roseville, California, factory — the company’s first U.S. semiconductor production facility and a $2 billion transformation of the former TSI Semiconductors site. The milestone comes after Bosch finalized a $225 million CHIPS Act subsidy agreement with the U.S. Commerce Department, as reported by Reuters on July 13, 2026.
As @everything_PE_ posted on X: “Bosch has begun sample production of SiC chips at its Roseville, California facility, marking a significant milestone in strengthening U.S.-based semiconductor manufacturing.” The City of Roseville noted on X that Bosch’s $1.9 billion investment will make approximately 40% of all U.S.-manufactured SiC chips at this single site. Commercial production is expected later in 2026.
For engineers, packaging teams, and supply-chain leaders in defense electronics, aerospace, automotive, and high-reliability manufacturing, the Bosch Roseville story is worth understanding — not just as a headlines-level investment announcement, but as a case study in what domestic semiconductor manufacturing actually requires beyond the cleanroom door.
Silicon carbide is a different beast than logic or memory
Silicon carbide chips manage high-voltage electricity. They convert DC to AC in electric vehicle drivetrains, regulate power distribution in data centers, and — critically for defense — enable high-efficiency power conversion in radar systems, electronic warfare platforms, directed-energy weapons, and space-based systems where thermal performance and radiation tolerance are non-negotiable. As Bosch North America CEO Paul Thomas told Reuters, the applications extend beyond automotive into “data centers” and “defense applications.”
Unlike advanced logic nodes where the primary challenge is transistor density, SiC device manufacturing presents distinct process challenges that directly affect yield, reliability, and field performance:
- Substrate defect sensitivity: SiC wafers contain crystal defects — micropipes, threading screw dislocations, basal plane dislocations — at rates orders of magnitude higher than silicon. These defects propagate through epitaxial growth and directly cause device failures. Contamination control at every process step is critical to preventing yield loss and latent reliability failures.
- Metallization and contact integrity: Ohmic contacts on SiC require specific surface preparation sequences. Any contamination residue from prior cleaning steps can create contact resistance variability that degrades device performance — particularly problematic in high-voltage power applications where localized heating accelerates failure.
- Wire bonding and packaging thermal demands: SiC devices operate at junction temperatures up to 200°C or higher. Wire bond interfaces, die-attach materials, and encapsulation must survive thermal cycling that would destroy conventional silicon assemblies. The packaging process itself must meet reliability standards matching or exceeding the die.
- Edge termination and passivation cleanliness: SiC device edge structures require precise surface preparation. Ionic contamination at the die edge creates leakage paths that compromise high-voltage blocking capability — a failure mode that may not appear in initial testing but manifests under field stress.
The $2 billion fab is step one. The process ecosystem is what makes it work.
Bosch’s Roseville facility has 130,000 square feet of cleanroom space. At full capacity, it will produce the majority of Bosch’s total SiC IC output. But a fab producing SiC die is only the upstream node in a supply chain that must deliver qualified, reliable SiC devices into finished electronic assemblies — for vehicles, data centers, radar systems, and power conversion platforms.
The downstream process chain — die preparation, wire bonding, die attach, power module assembly, thermal management, testing, and qualification — is where domestic capability either holds or breaks. This is the process layer that SEMI’s 2026 U.S. Policy Strategy identifies as critical to sustaining semiconductor leadership, alongside trade policy, export controls, workforce development, and R&D continuity.
The EE Times analysis on reshoring semiconductor manufacturing quantifies the challenge: U.S. fabs cost approximately 30% more to build and operate than those in Taiwan, South Korea, or Singapore — and up to 50% more than those in China. Every yield loss, every rework cycle, every reliability failure detected at incoming inspection rather than at the process step where it was introduced erodes the economic case for domestic production. SIA projects $650 billion in U.S. semiconductor investment over the coming decade, with fabs employing roughly 115,000 people — but estimates 67,000 positions could go unfilled without workforce development action.
The FAR Council’s proposed rule implementing Section 5949 — prohibiting federal agencies from purchasing products containing semiconductors from designated Chinese entities, set to take effect December 2027 — adds procurement urgency. For defense and aerospace OEMs, EMS providers, and hybrid microelectronics shops, this means full BOM traceability from die through final assembly. A domestically produced SiC die only satisfies the procurement requirement if every downstream process step can also be documented and audited.
What the process layer requires in practice
For senior process engineers, semiconductor packaging teams, aerospace and defense electronics suppliers, and federal supply-chain stakeholders, the specific domestic process challenges that a fab like Bosch Roseville creates downstream include:
- Contamination control at tighter specifications: SiC power devices operate at higher voltages and temperatures than silicon counterparts. Ionic contamination, particulate residue, and flux contamination that might be tolerable in a consumer-grade silicon assembly become reliability risks in SiC power modules. The cleaning and passivation processes applied to SiC die and packaging substrates must meet correspondingly tighter specifications — and those processes must be qualified, repeatable, and documented.
- Component preparation for legacy and constrained devices: Defense and aerospace systems that will use domestically produced SiC power devices also rely on legacy components — older-generation processors, memory, RF devices, and analog components — that will not come from a new SiC fab. Reconditioning, tinning, lead forming, and solderability restoration of these constrained components remains a domestic manufacturing necessity.
- Wire bonding and microelectronics packaging: SiC power module assembly demands gold or aluminum wire bonds capable of surviving thermal cycling to 200°C+. Bond quality, surface condition, and process cleanliness directly determine yield and field reliability. This is particularly critical for defense programs where latent bond failures can have mission-critical consequences.
- Thermal and vacuum process equipment: Controlled heating, curing, outgassing, and environmental stress screening of SiC assemblies requires equipment capable of maintaining precise temperature profiles across the assembly. Thermal processing that introduces stress or contamination at this stage can negate the value of a domestically produced die.
- Bill-of-materials traceability: Section 5949 requires documentation that every semiconductor in the BOM — across every sub-assembly and sub-tier supplier — can demonstrate provenance outside designated foreign entities. For SiC power modules with multiple die, substrates, and interconnect materials, this traceability challenge extends well beyond the fab.
Where Akrivis supports the domestic process ecosystem
Akrivis supports U.S. and North American manufacturers building or strengthening domestic electronics process capability. We do not claim that every product we represent is Made in USA, Buy American compliant, or federally compliant — those determinations are legal and procurement-specific and must be independently verified for each program.
What we do is help manufacturers evaluate and source the process equipment and application support needed to turn a domestic facility into a qualified, high-reliability production operation. That work spans:
- Cleaning and contamination-control systems — vapor degreasing, aqueous cleaning, and controlled process review for PCB/SMT, microassembly, hybrid microelectronics, power module assembly, and precision component applications — evaluated for compatibility, residue removal, throughput, and EHS compliance.
- Component preparation equipment — lead forming, lead cutting, component tinning, solderability recovery, and legacy component reconditioning — critical for defense and aerospace programs working with constrained or long-life components alongside newly produced domestic die.
- Wire bonding and microelectronics packaging support — process discussions, equipment evaluation, and application review for high-reliability SiC and power module assemblies where bond quality and surface condition directly determine yield and field reliability.
- Thermal and vacuum process equipment — controlled heating, drying, curing, outgassing, and environmental stress screening of sensitive electronic assemblies, including SiC power modules operating at elevated junction temperatures.
- North American application support — the engineering and service presence that makes domestic process capability sustainable, not just aspirational.
The investment in domestic SiC production at Roseville is real — $2 billion, CHIPS Act backing, commercial production targeted for 2026. But the fab output must flow through a process ecosystem that is equally capable, equally documented, and equally domestic. For manufacturers evaluating process equipment, qualifying assembly processes for defense-grade reliability, or building traceability for federal BOM compliance, the question is not whether the die is made in America. It is whether the entire process chain — from cleaning through final assembly — can deliver the reliability and documentation that domestic procurement demands.
For manufacturers navigating this transition, Akrivis can help assess your application requirements and process equipment needs.
Sources
@everything_PE_ on X — “Bosch has begun sample production of SiC chips at its Roseville, California facility, marking a significant milestone in strengthening U.S.-based semiconductor manufacturing.”
@CityofRoseville on X — “Bosch’s $1.9 billion investment is strengthening Roseville’s role… make ~40% of U.S. SiC chips.”
Reuters: “Bosch begins sample production at its first US semiconductor plant,” July 13, 2026 — $225M CHIPS Act funding finalized; $2B total investment; 130,000 sq ft cleanroom; commercial production later in 2026; Bosch plans up to $7.5B in U.S. investments through 2031.
Electronics Weekly: “Bosch starts semiconductor production in US,” July 14, 2026 — Fab will produce majority of Bosch’s total SiC ICs and over 40% of all U.S.-manufactured SiC chips at full capacity.
SEMI 2026 U.S. Policy Strategy (PDF), January 2026 — Five interconnected policy areas for sustaining U.S. semiconductor leadership including supply-chain resilience and workforce development.
FAR Council NPRM on Section 5949 Semiconductor Prohibition, February 17, 2026 — Proposed rule implementing prohibition on federal procurement of semiconductors from designated Chinese entities, effective December 2027.
EE Times: “Harnessing Data Is Paramount to Reshoring the Chip Industry” — Analysis of U.S. fab cost premiums (30-50% above Asian counterparts), SIA $650B reshoring projection, and 67,000 unfilled semiconductor workforce positions.