GlobalFoundries’ Two New Malta Fabs and the First U.S. Silicon Interposer: Why ‘Made in America’ Is a Process-Capability Story

The reshoring story has been told mostly in headline numbers: megafabs, DRAM commitments, and advanced-packaging campuses. Two announcements out of upstate New York in the past week put a sharper, more process-specific point on it. On October 14, 2026, GlobalFoundries was selected as technology provider and operator for two new semiconductor fabs at its Malta, New York campus under a U.S.-Japan initiative providing up to $21 billion in funding. The same day, the U.S. Department of Commerce’s CHIPS Program Office amended GlobalFoundries’ existing award to reallocate up to $955 million toward silicon photonics, silicon-germanium (SiGe), and advanced packaging at Malta and Burlington, Vermont. And on October 8, GF and TSMC announced a $2 billion, multiyear agreement to make Malta the first U.S.-based source of silicon interposers for TSMC’s CoWoS advanced packaging ecosystem.

For engineers who live in the back end of the line, the interposer piece is the one that matters most — and it is the one that most clearly shows why “Made in America” is a process-capability story, not a label. Trading-focused coverage on X put the scale in plain terms. Walter Bloomberg’s October 14 post summarized the $21 billion figure, the 27,000 construction and supply-chain jobs, the 1,000-plus manufacturing jobs, and the roughly 4% U.S. equity stake in GlobalFoundries. GlobalFoundries’ own account confirmed work is already underway on the first fab, with CEO Tim Breen telling Bloomberg that “every indicator I see today is flashing green around market demand.”

What the two fabs actually add

The first fab is a new 300mm line expected to come online in 2029, adding roughly 900,000 wafers of annual U.S. capacity; a second fab would add a comparable amount. These are “essential chips” — the less glamorous but structurally critical devices that go into vehicles, industrial equipment, communications gear, and the power and signal-conversion functions that surround every AI accelerator. The project is expected to create about 27,000 construction and ecosystem jobs and more than 1,000 high-skilled manufacturing jobs in New York’s Capital Region. The U.S. Commerce Department’s stake in GlobalFoundries is set to rise from 3% to 7%.

But the deeper signal is in the $955 million CHIPS amendment. It accelerates domestic capacity for silicon photonics, SiGe, and — critically — advanced packaging, including the first U.S.-based source of silicon interposers supporting advanced packaging technologies, with embedded deep trench capacitor components. That is not a headline number; it is a specific manufacturing capability being stood up onshore.

Why the silicon interposer is the real bottleneck

Here is the context every packaging engineer already knows: the U.S. can now fab advanced wafers in Arizona, but most advanced packaging — specifically TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) — is still done in Taiwan. Every accelerator built at the Phoenix fab still travels to Taiwan for CoWoS packaging before it can ship, and domestic CoWoS capacity from Amkor’s Arizona site and TSMC’s own planned packaging fabs is not expected to begin production until at least 2028. The interposer is the silicon substrate that sits between the logic die and the package substrate in a 2.5D stack, carrying through-silicon vias and deep trench capacitors that route power and signals across the package. It is the physical bridge that makes heterogeneous integration work.

Under the GF-TSMC agreement, GF will provide manufacturing service to TSMC and add fabrication capacity at Malta, with volume production expected to begin ramping in the first half of 2028. As Manufacturing Dive noted, this is the first U.S.-based source of silicon interposers for the CoWoS ecosystem — a step toward closing the loop where wafers no longer have to leave the country to be finished. That is the difference between “made in America” as a procurement checkbox and “made in America” as an actual, working supply chain.

An interposer is a process capability, not a label

Standing up a U.S. silicon interposer line is not a matter of stamping a flag on a wafer. It is a demanding set of process disciplines, and each one maps to the kind of work process engineers actually do:

  • Contamination control decides yield and reliability. Interposers carry high-density through-silicon vias and deep trench capacitors; ionic contamination and surface residue directly threaten via integrity, dielectric behavior, and long-term reliability. Cleaning and surface-preparation processes — measured ionic residue, SIR-verified wet chemistry, controlled rinse and dry — are gates for any advanced-packaging program, not afterthoughts.
  • Microassembly and die stacking are dominant modes. 2.5D/3D integration depends on die-to-interposer attach, underfill, and void-free bond lines. A trapped void or a marginal attach is a latent reliability failure in a package that must survive thermal cycling in data-center and defense environments.
  • Wire bonding and interconnect discipline. Fine-pitch and high-density interconnects depend on surface condition, tooling, and a documented process window. Bond integrity and pull/shear strength must be characterized and traceable to meet the qualification and surveillance expectations of aerospace, defense, and high-reliability buyers.
  • Solderability and component preparation. Re-sourced and alternate-sourced components under a new domestic supply source share the same problem as every re-sourced device: tired leads, oxide, and mixed metallizations. Solderability verification per J-STD-002, controlled re-tinning, and repeatable lead forming keep a new-sourcing qualification from failing first article.
  • Thermal and vacuum process control. Curing, vacuum-assisted die attach and underfill, and controlled reflow profiles all live in this line. Documented thermal/vacuum profiles are the difference between a package that is “made” and one that is qualified.
  • Traceability, not art. A package destined for defense, grid, or AI-infrastructure programs needs provenance that ties a part to a validated process run: equipment parameters, cleaning-bath chemistry and logs, bond and thermal profiles, and controlled rework history. The supply-chain resilience the federal programs are buying is only as strong as that record.

What this means for domestic electronics manufacturers

The Malta announcements are part of a broader pattern: federal incentive money is now being tied to actually-rolling domestic production lines, and the advanced-packaging gap is being treated as the strategic bottleneck it is. For EMS providers, semiconductor packaging teams, RF/microwave and hybrid microelectronics groups, and aerospace/defense electronics suppliers, the practical consequence is that onshore process capability — not a label — is what will decide who qualifies for the programs these investments feed. The wafers and interposers may be American; the qualification burden is real, and it lives in the back end.

Akrivis supports U.S. and North American electronics manufacturers building that domestic process capability — cleaning and contamination control, PCB/SMT and microassembly cleaning, vapor degreasing, component lead forming and cutting, legacy component reconditioning and tinning, solderability, wire bonding, and thermal and vacuum process equipment, backed by North American application support. Our application engineers work with semiconductor packaging groups, EMS providers, and aerospace/defense electronics suppliers on the process questions that decide whether an onshore device or package becomes a qualified, field-reliable product.

Request an application review to walk through your cleaning, attach, bonding, solderability, or thermal process challenges with an Akrivis application engineer. Visit /contact/ to start.

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